I am trying to repeat the pipetest example using the HDL code provided in the Samples folder after FrontPanel installation.
I add all the necessary modules, .v files and .ngc files.
I receive an error in synthesis step saying:
[Synth 8-3966] non-net port ep_clk cannot be of mode input: `default_nettype is “none” [“X:/XEM7350/jj/jj.srcs/sources_1/imports/XEM7350-K160T/okLibrary.v”:146]
Do you have any idea why is this happening?