In my first attempt at a design, which is a modified version of the “First.vhd” example, I have ep25 setup as an okWireOut and I have a 32-bit counter connected to it, so that ep25 returns to the PC the lower 16 bits of the count.
During the mapping phase of the “Implement design” procedure, I get a strange error message, like this:
ERROR:MapLib:661 - BUFT symbol “ep20/ti_data_wirehold_0” (output
signal=ti_data, enable signal=ep20/ti_data_wirehold_N0) has input
signal “ep25/wirehold” which will be trimmed. See the trim report for
details about why the input signal will become undriven.
I couldn’t make head or tail of this, so I started searching on the Xilinx website, and as advised in answer record #23990, I had a look at the trim report. Everything seems OK in the trim report except for one line that I can’t explain:
The signal “ep25/wirehold” is sourceless and has been removed.
What does this mean? Since I don’t have the vhdl code for the okWireOut module (it comes as an NGC I think), I’m unable to come up with any further theories. Can someone more knowledgeable please come to my rescue?
Note: The message about “ep25/wirehold” appears in the initial section of the trim report and is not indented. Underneath in the second section, indented, it then proceeds to optimize away most of my design… but it looks like the problem with “ep25/wirehold” signal is the underlying cause.