Starting with HDL


#1

Hi Jake!

I am a fresh owner of XEM3001. Thank you for publishing a tutorial for XEM.
I never programmed HDL before, but I do work with Protel DXP and downloaded Xilinx ISE. I managed to compose, compile and download some code with ISE schematic top level design. I tried to add the XEM communication library (VHDL) by compiling modules to schematic but I encountered problems. Functionality of blocks remains mistery to me.

Is it possible to use this approach (working with schematics), because for me it is easier to visualise?
Which low level language do you recommend (Verilog or VHDL)?
Is Protel DXP better (easier) for programming FPGAs than ISE?

Thank in advance you for answer,

Alex


#2

Alex-

First of all, welcome to the HDL arena. I personally don’t see much value in schematic-based design methodologies anymore since HDLs can accomplish the same thing (structural description) as well as behavioral description. HDLs also free you from proprietary netlist/file formats that may become useless if you don’t keep updated software.

That said, Verilog and VHDL are similar in many ways. Many experienced users tend toward VHDL because it has more features that are useful in some settings. I think learning Verilog is easier and less confusing from a syntax point of view and the later migration to VHDL is straightforward. Learning VHDL first involves a steeper curve.

I’ve never used Protel for FPGA design, only PCB design, so I can’t comment on that.

My suggestion is to start with Verilog and leave schematics behind. Teach yourself to visualize the behavior you want and learn how to describe it in HDL. Always remember that Verilog/VHDL are not software. They are hardware description languages. You’ll go a long way if you can look at HDL and visualize the circuit that will likely be synthesized.

There are many times where I will sketch a small schematic of gates, FFs, etc, to help visualize the functionality, then I describe the hardware in HDL. Or, I’ll sketch a timing diagram and do the same. They should all eventually become equivalent ways to accomplish a result.

Cheers,
Jake


#3

Thank you for your answer Jake!

I appreciate immediate response. I am C++ user an I hope I can switch to HDL. I’ll try to learn VHDL and if I have some more problems I’ll contact you.

Thanks,

Alex


#4

Hi Jake!

I tried Protel DXP Schematics, but I think I will not work with XEM. So I learned VHDL (just a little bit) and for start I also work with schematic in ISE.
I have serious problems with understanding the functionality of modules in okLibrary.vhd. Is it possible to get detailed description(functionality and port description) of modules in that library? Otherwise I cannot compose my own program and especially simulate it.

Thanks


#5

Hello-

The FPGA modules (contained within okLibrary) are documented in the FrontPanel User’s Manual. There are also a few samples as well as an online tutorial to help you get started. If you have a specific question, you can post it here.

Cheers,
Jake


#6

Hi Jake!

I read the FrontPanel user manual and indeed it provides lots of information. But I want a little more on okBufferedPipeOut. Thing works, but I have some sync problems. Does the okBufferedPipeOut writes EP_DATAIN at EP_CLK low-to-high transition if EP_WRITE is high? Does EP_RESET resets pointers for input and output of FIFO at the same time at EP_RESET high-to-low transition or it is held under reset when EP_RESET is high?

Thanks

Alex


#7

Hi Alex-

The BufferedPipe design is based on a Xilinx asynchronous FIFO described in XAPP131:

http://www.xilinx.com/bvdocs/appnotes/xapp131.pdf

The FIFO has been slightly modified to accomodate the larger BRAMs available in the Spartan-3 series. The BufferedPipe is really just a structural description connecting the FIFO from this application note to the PipeIn or PipeOut module.

I will make a note of this in the documentation for the BufferedPipes as I think it may clear up some confusion to others, as well.

Cheers,
Jake