I am interested in creating a design that uses the Cypress EZ USB FX2LP and hooking it to an FPGA via Slave FIFO Mode. Is it possible to do this with the XEM3001 board? I don’t think it is, and I’m just looking for some confirmation.
I think there are a few needed pins that don’t seem to be hooked to the Spartan3 on the board, like FIFOADDR0, FIFOADDR1, PACKETEND. If I’m wrong, could you give me a pin# list of FX2LP pins that are connected to the FPGA? I’m a little confused by the changing of pin names between the Cypress documentation and your documentation. I know what some of them are based on your documentation, could you help me fill in the other blanks?
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FrontPanel Host Interface pins
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NET “hi_clk” LOC = “P79”; # IF_CLK
NET “hi_cs” LOC = “P57”;
NET “hi_rdwr” LOC = “P58”;
NET “hi_busy” LOC = “P81”;
NET “hi_irq” LOC = “P85”;
NET “hi_addr” LOC = “P61”;
NET “hi_addr” LOC = “P62”;
NET “hi_addr” LOC = “P63”;
NET “hi_addr” LOC = “P64”;
NET “hi_data” LOC = “P67”; # FD(0)
NET “hi_data” LOC = “P68”; # FD(1)
NET “hi_data” LOC = “P72”; # FD(2)
NET “hi_data” LOC = “P74”; # FD(3)
NET “hi_data” LOC = “P86”; # FD(4)
NET “hi_data” LOC = “P87”; # FD(5)
NET “hi_data” LOC = “P90”; # FD(6)
NET “hi_data” LOC = “P92”; # FD(7)
NET “hi_data” LOC = “P93”; # FD(8)
NET “hi_data” LOC = “P94”; # FD(9)
NET “hi_data” LOC = “P95”; # FD(10)
NET “hi_data” LOC = “P96”; # FD(11)
NET “hi_data” LOC = “P97”; # FD(12)
NET “hi_data” LOC = “P100”; # FD(13)
NET “hi_data” LOC = “P101”; # FD(14)
NET “hi_data” LOC = “P102”; # FD(15)