Hi,
I’m trying to source 8 internal ram blocks (each one belongs to a vhdl module and they are all identical) with the same ti_clk to achieve data transfers but sometimes I lose some data (specially the first and last words). I’m using the host interface clock (ti_clk) and put it through a DCM (only one) with a bufg output to feedback the DCM.
However, Xilinx ISE warns me that ti_clk may have significative clock skew [excessive clock skew] (it says that ok may suffer it also - what’s ok?). Is there a way to get no significant skew (minimize the skew) with them to get no skew Warnings anymore, please?
Thanks a lot,
Joao