Signal/pin assignment

Hi there!
I hope you can help me solve this issue, thanks in advance!
I am working with a XEM3010 module and have some unsolved stuff. I have already finished my development and it works well, the thing is I want to add test points using the FPGA disponible IO pins, but I have found something tricky. I set four test points, say L3, K2, K1 and K6, and I assign them certain internal signals (signals used in my VHDL code). When I do this, my design only works well when it comes from a power-on reset but when I reset the design (using a button conected to a pin) it either just break down or begins behaving oddly. When no test points are present my design works quite well.
Do you think it is somethig related to pin configuration (IOSTANDARD, SLEW RATE, DRIVE, etc… )?
may be I am assigning signals wrongly…
any idea, suggestion?


Your reset is a signal that drives your state machines and such?

If you’re using an asynchronous reset, I would advise converting this to a synchronous reset so that things are a little better defined. That way, you can be assured that everything is getting reset at the same time and, more importantly, LEAVING reset at the same time.

If your reset is asynchronous and has a large fanout, you can see (FPGA Editor) that there will be quite some distribution in how the reset is delayed through routing. In many cases, this can span multiple clock cycles and cause some funky action.