I’ve recently begun working with existing OpalKelly code that was written by others, none of whom are with the company any longer. We use the XEM3050 for rapid hardware development, and create C test programs using the API for verification.
Several VHDL modules are instantiated that use one or two WireIn modules to load configuration data when activated by a TriggerIn module. Some of the modules use the same addresses for their WireIn modules but have unique addresses for their TriggerIn modules. For example, a JumperConfig module uses WireIns with addresses 0x03 and 0x04 and a TriggerIn with address 0x41. A UartConfig module uses the same WireIn addresses but a TriggerIn with address 0x42. The VHDL modules are written such that the values present on the WireIns are only clocked into the FPGA when the appropriate trigger is activated. The software API is used to update the WireIn values and activate the TriggerIn at the appropriate time.
Per simulation results there doesn’t appear to be a problem; the proper modules are configured without bleeding into the other modules. Are there any possible problems with this approach? There are several files that may need to be modified if I start changing module addresses, so I’d like to avoid modifying the heritage code and introducing bugs if possible.
Thanks in advance,