Setting VCCO on Spartan 3E


#1

Does someone have an example of a UCF file that defines the value of VCCO_0, etc?

I would have thought that this was painfully simple, but I cannot figure it out.


#2

Bob–

It’s not so much that you define the value of VCCO. This is done at the board level by the voltage applied. What the tools need to know is what IO standard to apply to the pin. It then becomes your job to make sure your IO standard and VCCO voltage are appropriate – otherwise you may be able to damage the device.

Here’s an example:

NET “hi_in” LOC = “M8” | IOSTANDARD=LVCMOS33;


#3

As an aside, the Constraints Guide from Xilinx is very thorough on all this stuff. You were probably just looking in the wrong place, because it seems you were looking for a constraint on the VCCO pin, not the IO pin.


#4

Thanks for the reply.

Here is what I was trying to accomplish.

If I do not declare an IOSTANDARD, ISE assumes that the VCCO values are 2.5 V and it creates output pins that are LVCMOS25. If I declare one pin on a bank to be LVCMOS33 and if there are no other output pins on that bank, ISE shows VCCO to be 3.3 V for that bank and all is well. If there are other output pins on that bank for which I do not declare a standard, ISE wants to make those LVCMOS25 and then complains that there are inconsistent standards on that bank. I was hoping that there was some way to indicate to ISE that the VCCO values are 3.3 V for that bank, that it would make the pins all LVCMOS33 without explicit declarations. That’s what seems to be impossible.

So my choices seem to be to leave all the IOSTANDARDs undeclared on a given bank and let ISE assume 2.5 V standards, or to declare the IOSTANDARD for all pins on the bank, when the VCCO is 3.3 V. Is that right?


#5

Ah. I see.

Although I did not know this, this is probably just how ISE works.

In other words, it won’t let a single declaration change the default it applies to other pin constraints.