Im a bit confused by the fact the Windows program sets up the PLL for 133MHz yet timing in the HDL seems to be based around an 100MHz clock ?
It would be nice if the HDL for the SDRAM was documented as well, also if it was more flexible so that it could be used in any of the burst modes. Being a VHDL beginner (and no verilog) this is proving very difficult for me and is actually a major distraction from the job at hand. All I really want to be able to do is use the memory like I would an SRAM. Im not really interested in SDRAM contollers. I had sort of assumed that Opal Kelly would have provided a fully functional, documented controller for the SDRAM