SDRAM Controller


#1

Im a bit confused by the fact the Windows program sets up the PLL for 133MHz yet timing in the HDL seems to be based around an 100MHz clock ?

It would be nice if the HDL for the SDRAM was documented as well, also if it was more flexible so that it could be used in any of the burst modes. Being a VHDL beginner (and no verilog) this is proving very difficult for me and is actually a major distraction from the job at hand. All I really want to be able to do is use the memory like I would an SRAM. Im not really interested in SDRAM contollers. I had sort of assumed that Opal Kelly would have provided a fully functional, documented controller for the SDRAM


#2

Unfortunately, SDRAM is not quite that easy. SDRAM provides many benefits over SRAM (size, in particular) but, as you’ve noticed, at the expense of developing for its access modes.

Also, SDRAM is complex enough that one size does not fit all when referring to controllers. Some (like our sample) are very fast, small, and effective for a number of tasks. Others are available which provide access to many (or all) of the SDRAM modes but are complex enough to require a controller to interface to the controller! Xilinx has some application notes describing interfaces to various types of SDRAM.

Another you may be interested in is available here:

http://www.xess.com/ho03000.html

It was developed by Xess for use with their evaluation boards. It makes an SDRAM look like SRAM, but at the cost of performance. It was coded in VHDL.


#3

I should also note that some controllers are available for purchase through Xilinx and their alliance partners. This may be an option for you if you do not have the time to develop one on your own.

We are also available for contract work and could put something together for you. Please contact support@opalkelly.com if you’re interested.


#4

I’ve been simulating the contributed VHDL version of the sample SDRAM controller using a memory model from the Free Model Foundry. It complains about the device not being initialized properly. Taking a brief look at the code of the SDRAM controller, it appears there is no provision for the special initialization phase that many (all?) SDRAMs require (wait 100 us, two AUTO REFRESH cycles, etc.). It may be that the devices actually work in real life without this, but I just want to confirm that this was indeed left out of the code. (The original Verilog code came from Opal Kelly). Was the intention that we should use some software approach to performing the initialization? Thanks.


#5

— Begin quote from jadwin79;1112

I’ve been simulating the contributed VHDL version of the sample SDRAM controller using a memory model from the Free Model Foundry. It complains about the device not being initialized properly. …

— End quote

Oops, my mistake, there appears to be some init code in there after all. My memory model is complaining about DQMH/L being in the wrong state during initilization, and about a command being issued before power up is complete. I’m guessing at least some of this is model-specific and will track it down.