Is the SDRAM clock hard wired to the PLL ? looking at the examples I cannot see where it gets its clock from. Cheers.

I see that this is not clearly indicated anywhere in the XEM3010 User’s Manual. An update will be forthcoming.

The SDRAM on the XEM3010 (assuming you’re referring to the XEM3010) has its CLK input hard wired to SYS_CLK1 (CLKA on the CY22393 PLL). Note that this clock is shared with FPGA pin GCLK3 (location N9).