Is there a global reset available as an input to the FPGA? I know I could add one on JP2/JP3, but I was wondering if there’s a reset generator already on the board.
What do you mean by reset?
Do you want to reset the FPGA? If so, the configuration would need to be either downloaded by PROM or via USB. By PROM, you can insert jumper J2 and pressing S1 will reset the FPGA and reconfigure. By USB, the reset is delivered by the firmware when a reconfigure is initiated.
If you are talking about resetting your logic, then you can either deliver a reset signal from your add-on board (if you have one) or from either of the two pushbuttons. (note these are not debounced)
[QUOTE=Opal Kelly Support]What do you mean by reset?
Do you want to reset the FPGA? If so, the configuration would need to be either downloaded by PROM or via USB. By PROM, you can insert jumper J2 and pressing S1 will reset the FPGA and reconfigure. By USB, the reset is delivered by the firmware when a reconfigure is initiated.
If you are talking about resetting your logic, then you can either deliver a reset signal from your add-on board (if you have one) or from either of the two pushbuttons. (note these are not debounced)[/QUOTE]
OK, thanks, that tells me what I need to know. I was talking about a separate signal that resets the logic in the FPGA without requiring reconfiguration. Other boards I’ve used had a reset signal that came from a power supply supervisor chip that issued the reset in response to either a power-low condition or an external input to the supervisor chip.
Having a global reset for FPGAs is somewhat controversial – I think it’s standard ASIC practice, where you can’t guarantee the initial state of flip flops, but there are good arguments for not having one in an FPGA (since the flops come up in known states after configuration). I’ll eventually just go the PROM/S1 route you mentioned for a full reconfig.
Well the nice thing about an ASIC is that the design is still there if the power drops. This may or may not be the case with an FPGA depending on the degree to which the power drops. In this sort of case, it would probably be better to have an external supervisor monitor power and reconfigure the FPGA if things do, indeed, go that wrong.
Does S1 need to be pressed and released or can it be hardwired closed? In my system the XEM3010 has to work on it’s own and configure itself at powerup.
[QUOTE=Opal Kelly Support;825]What do you mean by reset?
Do you want to reset the FPGA? If so, the configuration would need to be either downloaded by PROM or via USB. By PROM, you can insert jumper J2 and pressing S1 will reset the FPGA and reconfigure. By USB, the reset is delivered by the firmware when a reconfigure is initiated.
If you are talking about resetting your logic, then you can either deliver a reset signal from your add-on board (if you have one) or from either of the two pushbuttons. (note these are not debounced)[/QUOTE]
Frank-
On the XEM3010, the PROG_B is only accessible via the button.
However – when setup for PROM programming, the device will configure from PROM on powerup.
All you need to do is setup the PROM with a valid bitfile (see the XEM3010 User’s Manual) and remove jumper J1 for PROM boot. The XEM3010-1500P can then be used in a standalone configuration.