Has anyone been able to use the RAMTEST HDL and get a successful compile, synthesis, implementation with XILINX ISE 14.2? I keep getting an error which I cannot figure out??

This happens when I simply try process --> implement top module

I eventually need to convert the code to VHDL, and know there is a thread with VHDL for the XEM-3010, but the 6010 has the integrated memory I/F controller so its VHDL would be very different.

Here is the error I am getting when compiling.

ERROR:Pack:2907 - The I/O component “clk1” has an illegal IOSTANDARD value. The
IOB component is configured to use differential signaling and can not use
single-ended IOSTANDARD value LVCMOS33. Two ways to rectify this issue are:

  1. Change the IOSTANDARD value to a differential standard. 2) Correct the I/O
    connectivity by instantiating a single-ended I/O buffer.


This problem was solved by two modifcations, and note, I am using ISE version 14.2, and targeting an XEM-6010-LX150 part. I eventually need to convert this code to VHDL but wanted to re-use what Opal-Kelly had done with the MCB memory interface to save time…

There were two problems:

  1. I was using the wrong version of memc3_infrastructure.v and should have used the version is the higher directory, not the version in MIG.

  2. The lines in ramtest.V starting with line 251 thru 256 needed to be removed…

Or the lines in memc3_infrastructure # starting with:


And ending with


Needed to be removed.