Has anyone been able to use the RAMTEST HDL and get a successful compile, synthesis, implementation with XILINX ISE 14.2? I keep getting an error which I cannot figure out??
This happens when I simply try process --> implement top module
I eventually need to convert the code to VHDL, and know there is a thread with VHDL for the XEM-3010, but the 6010 has the integrated memory I/F controller so its VHDL would be very different.
Here is the error I am getting when compiling.
ERROR:Pack:2907 - The I/O component “clk1” has an illegal IOSTANDARD value. The
IOB component is configured to use differential signaling and can not use
single-ended IOSTANDARD value LVCMOS33. Two ways to rectify this issue are:
- Change the IOSTANDARD value to a differential standard. 2) Correct the I/O
connectivity by instantiating a single-ended I/O buffer.