Hi there,
I’m using a modified sdramctrl version of your RAMTest sample implementation (Verilog) and realized
that you are triggering on the negative edge of sdram_clk:
always @(negedge sdram_clk) begin
if (reset == 1’b1) begin…
As I got some timing errors in ISE, I changed negedge to posedge. This change lessened the number of
erros I got in ISE, but my implementation started showing some strange behaviour that it didn’t show while using
negedge. So, my question is, what is the reason for using negedge as trigger for the RAMTest module?
Thanks.