Ramb16_s18_s18 core

Spartan-3 USB 2.0 Modules
1

Hi

I’m working on pipetest for my design. I don’t have the Ramb16_s18_s18 in my IP Cores in Xilinx 7.1i

How can I add this bolck ram to my program? Do you know where I could find this file?

Thanks
Sam

2

Sam-

This would seem to be a problem with your ISE 7.1i installation. You may want to look through the Xilinx Answer Browser to see if there is some mention of this.

3

I’ve tried to implement my design on few different computers. I don’t think that is an installation problem because I don’t have any xco or vho file in my pipetest’s folder. I think that’s why I can’t use this ramb16_s18_s18…

Could you send me that file if you have it? Here is my email adress : [email protected]

Thank you, it’s very urgent

Sam

4

We have a look at the IP core generator
We work with the last ISE version: 8.1 Fundation
We select
memory and storage elements
rams and roms
dual port block memory

looking in different versions 5.0 6.0 …
we find different versions but none have the same inputs (DIA DIPA SSRA) than the one you use in your sample project (pipetest).

We are unable to make the same program starting from crash. Our application is very similar to this sample so we try to build it again.

If you can help
thx