Question regarding XEM5010 Quick Reference

In the XEM5010 UG, on pages 20-23. In the FPGA LVDS column. They are labelled with notations, that I am unable to cross reference with the vertex5lx UG.

Can you tell me what the following in those columns means:
*]SMxP/N, where x goes from 0 to 8.

I also want to know what these notations mean or at least where to find out

Please see the Virtex-5 pinouts documentation from Xilinx. This describes the I/O naming conventions.