Hello,
Consider the situation where a BTPipeIn is halted and information is ready to be sent back to the computer using PipeOut. Is it possible to do this PipeOut call while the BTPipeIn is halted, or does the BTPipeIn not allow this? In other words, will I have to end the BTPipeIn “connection” (which is currently “paused” waiting for EP_READY to be asserted) to make a PipeOut call in this type of situation?
Thanks in advance,
Vitor
No. Only one call is allowed at a time. You will need to multiplex your calls a bit differently to send two streams through.
— Begin quote from Opal Kelly Support;2001
No. Only one call is allowed at a time. You will need to multiplex your calls a bit differently to send two streams through.
— End quote
hello, I was wondering if you coud please elaborate some more about your answer on multiplexing my calls a bit differently to send two streams through? how would these work in order to make it possible?
Thank you again,
Vitor
Vitor–
You need to time-division-multiplex your calls:
PipeIn on 0x80
PipeIn on 0x81
PipeIn on 0x80
PipeIn on 0x81
…
Or, if you know ahead of time that your data has structure you can multiplex, you can use the FPGA to combine streams. For example, if one stream had 3x the bandwidth requirement of another stream, you could do something like this:
A0 A1 A2 B0 A3 A4 A5 B1 A6 A7 A8 B2 …
Then use the PC to separate the streams.
Hello again,
Unfortunately, the cases you described do not relate to the problem I had in mind when I started the thread; maybe I expressed myself wrong. This is what I want to know: let’s say my pipein is constantly feeding the module with data, and the results are being saved to a RAM. when the ram is full, I’m going to have to stop the pipein to make a pipeout, so I can clear space on the ram for more output data. This is what I first wanted to know: Is there any way I can momentarily stop the PipeIn ( Maybe something related to BTPipeIn ), do a PipeOut and then continue the PipeIn from where it stopped?
Keep in mind my main goal here is to reduce the time spent on transfers, so I can maximize my project’s performance.
Furthermore, let’s say I have a module that processes data 64 bits at a time. If my PipeIn can only provide me 16 bits of data at a time, this means that I am going to need 4 cycles of PipeIn to fill up the datain for my module, which means that my module will only process data at every 4 cycles. Is there anyway I can provide more than 16 bits of data at a time as to circunvent this?
Thank you very much for your patience so far answering my questions,
Vitor
— Begin quote from vitorbal;2042
This is what I first wanted to know: Is there any way I can momentarily stop the PipeIn ( Maybe something related to BTPipeIn ), do a PipeOut and then continue the PipeIn from where it stopped?
Keep in mind my main goal here is to reduce the time spent on transfers, so I can maximize my project’s performance.
— End quote
No, you cannot stop a process in progress. But if you use the SDRAM, you’ve got 32 MB to work with. Transfer sizes around 1 MB and bigger are near the peak bandwidth.
— Begin quote from vitorbal;2042
Furthermore, let’s say I have a module that processes data 64 bits at a time. If my PipeIn can only provide me 16 bits of data at a time, this means that I am going to need 4 cycles of PipeIn to fill up the datain for my module, which means that my module will only process data at every 4 cycles. Is there anyway I can provide more than 16 bits of data at a time as to circunvent this?
— End quote
As you say, the pipe bus width is 16 bits. To process 64 bits you’ll need to transfer over 4 cycles.