Question about PC / FPGA interface

Spartan-3 USB 2.0 Modules
1

Looking at the example .cpp file in the DESTEST tutorial

from DESTester.cpp:

// Wait for the TriggerOut indicating DONE.
for (j=0; jUpdateTriggerOuts();
		if (xem->IsTriggered(0x60, 1))
			break;
	}
	if (j==10) {
		printf("DES did not complete properly.\n");
		return(false);
	}

It looks like the program expects the FPGA to finish its computation and assert a DONE trigger before 10 cycles in the for loop. How many CLK cycles does each UpdateTriggerOut() take?

THanks

2

UpdateTriggerOuts() is PC-based and it is indeterminate how many FPGA CLK cycles it will take. Typically, you should be able to execute around 1000 UpdateTriggerOuts per second, but this will vary depending on your PC setup.

3

Hi, we used PC to Parallel Port interface using a bidirectional transciever as shown here :

http://edge.kitiyo.com/2009/pc-interface-logic/interface-circuit-schematics.html
. It is kinda slow and would like to migrate to USB in future projects. Is there any open source cost free implementations out there ? as we are a academic group, cannot afford to buy the products. :slight_smile: