Hello,
I am having some problems with using the BufferedPipeOut component. I am attempting to sample data to send to the PC, but ReadFromPipeOut is always returning -1. Below is my hdl code, stripped for example purposes:
[CODE]
– standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
– Xilinx primitive components
library UNISIM;
use UNISIM.VComponents.all;
entity Test is
port
(
hi_clk : in STD_LOGIC;
hi_cs : in STD_LOGIC;
hi_rdwr : in STD_LOGIC;
hi_busy : out STD_LOGIC;
hi_irq : out STD_LOGIC;
hi_addr : in STD_LOGIC_VECTOR(3 downto 0);
hi_data : inout STD_LOGIC_VECTOR(15 downto 0);
CLK : in std_logic;
O_CLK : out std_logic;
RESET : in std_logic;
IO : inout std_logic_vector(7 downto 0);
O_IO : inout std_logic_vector(7 downto 0);
--LED0 : out std_logic
led : out std_logic_vector(7 downto 0)
);
end Test;
architecture rtl of Test is
component okHostInterface port (
hi_clk : in std_logic;
hi_rdwr : in std_logic;
hi_cs : in std_logic;
hi_irq : out std_logic;
hi_busy : out std_logic;
hi_addr : in std_logic_vector(3 downto 0);
hi_data : inout std_logic_vector(15 downto 0);
ti_clk : out std_logic;
ti_control : out std_logic_vector(12 downto 0);
ti_data : inout std_logic_vector(15 downto 0));
end component;
component okWireOut port (
ti_clk : in std_logic;
ti_control : in std_logic_vector(12 downto 0);
ti_data : out std_logic_vector(15 downto 0);
ep_addr : in std_logic_vector(7 downto 0);
ep_datain : in std_logic_vector(15 downto 0));
end component;
component okBufferedPipeout
port (
ti_clk : in std_logic;
ti_control : in std_logic_vector(12 downto 0);
ti_data : out std_logic_vector(15 downto 0);
ep_addr : in std_logic_vector(7 downto 0);
ep_clk : in std_logic;
ep_reset : in std_logic;
ep_write : in std_logic;
ep_datain : in std_logic_vector(15 downto 0);
ep_full : out std_logic;
ep_empty : out std_logic;
ep_status : out std_logic_vector(3 downto 0)
);
end component;
signal ti_clk : STD_LOGIC;
signal ti_control : STD_LOGIC_VECTOR(12 downto 0);
signal ti_data : STD_LOGIC_VECTOR(15 downto 0);
signal ep20wire : STD_LOGIC_VECTOR(15 downto 0);
signal ep21wire : STD_LOGIC_VECTOR(15 downto 0);
signal ep22wire : std_logic_vector(15 downto 0);
signal pipe90Data : std_logic_vector(15 downto 0);
signal pipe90Reset : std_logic;
signal pipe90Write : std_logic;
signal pipe90Full : std_logic;
signal pipe90Empty : std_logic;
signal pipe90Status : std_logic_vector(3 downto 0);
signal byte_count : std_logic_vector(31 downto 0);
begin
– Instantiate the okHostInterface and connect endpoints to
– the target interface.
okHI : okHostInterface port map (
hi_clk => hi_clk,
hi_rdwr => hi_rdwr,
hi_cs => hi_cs,
hi_irq => hi_irq,
hi_busy => hi_busy,
hi_addr => hi_addr,
hi_data => hi_data,
ti_clk => ti_clk,
ti_control => ti_control,
ti_data => ti_data
);
--2 wires to pass the number of transferred bytes
ep20 : okWireOut port map (
ti_clk => ti_clk, ti_control => ti_control, ti_data => ti_data,
ep_addr => x"20", ep_datain => ep20wire);
ep21 : okWireOut port map (
ti_clk => ti_clk, ti_control => ti_control, ti_data => ti_data,
ep_addr => x"21", ep_datain => ep21wire);
ep20wire ti_clk,
ti_control => ti_control, ti_data => ti_data, ep_addr => x"90",
ep_clk => clk_buf, ep_reset => pipe90Reset, ep_write => pipe90Write,
ep_datain => pipe90Data, ep_full => pipe90Full, ep_empty => pipe90Empty,
ep_status => pipe90Status);
pipe90Data(7 downto 0) CLK, O => clk_buf );
clk_obuf : OBUF port map ( I => clk_buf, O => O_CLK );
-- LEDs
led(7 downto 0) in order to read a single byte, ret always comes back -1.
I am not sure how to proceed in resolving this issue. Any help will be greatly appreciated.
Thank you,
–Nathan Cain
P.S.
Could you please enable my access to the downloads area? Thaks.