I can’t get the ‘first’ example to compile. I have been able to get the Xilinx stopwath example to compile and I’m wondering if you can help.
I’m using the newest FrontPanel module in the XilinxISE71_v2 folder as well as the latest XEM3001v2-Verolig sample of ‘First’.
ISE 8.1i immediatly recognizes these as older version 7.1 files and does a conversion. Everything looks normal in the ISE tool except that it chokes when it gets to the Implement Design – Translate phase, there I get these error messages (see attached *.zip, look in First.bld for errors).
I suspect I need to fall back to ISE 7.1 or some new FrontPanel modules updated for ISE 8.1i but before I waste anymore time could you tell me what you think is wrong???
Thanks Shaun McMaster
First_XEM3001v2-Verilog.zip (321.8 KB)