Problems w/ ISE 8.1i


#1

hi,

I can’t get the ‘first’ example to compile. I have been able to get the Xilinx stopwath example to compile and I’m wondering if you can help.

I’m using the newest FrontPanel module in the XilinxISE71_v2 folder as well as the latest XEM3001v2-Verolig sample of ‘First’.

ISE 8.1i immediatly recognizes these as older version 7.1 files and does a conversion. Everything looks normal in the ISE tool except that it chokes when it gets to the Implement Design – Translate phase, there I get these error messages (see attached *.zip, look in First.bld for errors).

I suspect I need to fall back to ISE 7.1 or some new FrontPanel modules updated for ISE 8.1i but before I waste anymore time could you tell me what you think is wrong???

Thanks Shaun McMaster


First_XEM3001v2-Verilog.zip (321.8 KB)


#2

Shaun-

You do not need new NGC modules for 8.1i. However, I can tell you that I share your frustration with 8.1i. It doesn’t do the conversion very well and fails most of the time.

I suggest starting from “scratch” and creating a new project. Add you code, add your UCF file, add the okLibrary.v file, then add a path to the NGC file (unless you copy them directly to your project directory)


#3

I got 7.1 working, I realized my PCB was pretty old.

Even w/ 7.1 I had to start from scratch and copy all files into the project which seems silly.

I’ll try 8.1 againn tomorrow and see if now that I’m using the right frontpanel HDL if I can’t get that to work.

Thanks,
Shaun