yup, total newbie here. I’ve tried my best to resolve this problem by searching the forums and reading all the READMEs and pdf documentation, but alas, I’m at a loss.
after running the first example simulation, I get the errors:
WARNING:HDLCompiler:267 - “First_tf.v” Line 27: Cannot find port button on this module
WARNING:HDLCompiler:267 - “First.v” Line 53: Cannot find port hi_aa on this module
ERROR:HDLCompiler:25 - “First_tf.v” Line 32: Module “First” does not have a port named “button”.
WARNING:HDLCompiler:1016 - “First_tf.v” Line 27: Port hi_aa is not connected to this instance
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
I’ve check the verilog files, and indeed there is no “hi_aa” port in the module okHost, nor is there a “button” port in the module First.
what am I doing wrong?
edited to add the following (probably) relevant info:
Windows 7, 32 bit
Xilinx Webpack 13.1