yup, total newbie here. I’ve tried my best to resolve this problem by searching the forums and reading all the READMEs and pdf documentation, but alas, I’m at a loss.
after running the first example simulation, I get the errors:
WARNING:HDLCompiler:267 - “First_tf.v” Line 27: Cannot find port button on this module
WARNING:HDLCompiler:267 - “First.v” Line 53: Cannot find port hi_aa on this module
ERROR:HDLCompiler:25 - “First_tf.v” Line 32: Module “First” does not have a port named “button”.
WARNING:HDLCompiler:1016 - “First_tf.v” Line 27: Port hi_aa is not connected to this instance
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
I’ve check the verilog files, and indeed there is no “hi_aa” port in the module okHost, nor is there a “button” port in the module First.
what am I doing wrong?
edited to add the following (probably) relevant info:
Windows 7, 32 bit
XEM 6010-LX45
Xilinx Webpack 13.1
I think I may of found my problem. There are multiple versions of “First.v”, and they have different ports. Which one should I use for the example tutorial?
They’re all installed in a separate directory. It should be fairly self explanatory. If you are targetting an XEM6010 in Verilog, use the one in the folder “First/XEM6010-Verilog”.
My confusion (for what it’s worth) was caused by reading the README file in the directory:
C:\Program Files\Opal Kelly\FrontPanelUSB\Samples
which stated:
SIMULATION
=============
The following samples have associated simulation versions:
First (Verilog and VHDL)
DES (Verilog)
Simulation versions are setup very similar to an actual FPGA-targetted
project, but might differ in a specific detail or two. In particular:
Simulation projects have the additional “*_tf.v” file which
contains the test fixture and attaches the FPGA pinout to the
host simulation. The host simulation represents everything from the
FPGA host interface pins back to the PC application code.
So I went looking for the “First_tf.v” file, which I found in the directory:
Copy simulation files from the Frontpanel installation directory ($FRONTPANEL) to a working directory ($WORKDIRECTORY).
Copy verilog simulation sources from $FRONTPANEL/Simulation/Verilog to $WORKDIRECTORY/oksim
So I then copied those over. The problem was there are 2 First.v files (one in each directory), and they’re different - thus causing the port error problems.
I apologize, I’m not trying to be difficult. I’m just really confused.
So do I not copy over the First_tf.v file and the associated other files in the directory?:
C:\Program Files\Opal Kelly\FrontPanelUSB\Samples\First\Simulation-USB-Verilog
Your first post was regarding synthesis and has a few warnings / errors from the XST tool.
Your second post regarded simulation. There should only be one First_tf.v, though. So I’m confused about your statement: “So do I not copy over the First_tf.v file and the associated other files in the directory?”
We try to make things as consistent as possible between simulation and synthesis. It looks like we may need to update some README materials and maybe provide additional direction for simulation on the different boards.
I’m truly sorry for the confusion. I do appreciate your help, and I know it can be frustrating attempting to help novices such as myself.
In the directory
C:\Program Files\Opal Kelly\FrontPanelUSB\Samples\First\XEM6010-Verilog
there are the following files: First.v
xem6010.ucf
and in the directory
C:\Program Files\Opal Kelly\FrontPanelUSB\Samples\First\Simulation-USB-Verilog
there are the following files:
first.do First.v
first_isim.bat
first_isim.prj
first_isim.tcl
First_tf.v
README.txt
My confusion lies with the fact that there are 2 “First.v” files, and they are different with respect to their port configurations. So when I followed the instructions of the README file and copied all the files from the Simulation directory into my working directory, I got the port errors when running fuse with the batch file “first_isim.bat” in the command line.
