I’m using an XEM6310 board, with 1.8 firmware and Front Panel v4.2.6.
I’m currently working on a design that is derived from the PipeTest example. In the FPGA, I implemented 2 FIFOs : one being filled while the other is being read through a PipeOut. When, say, FIFO1 is filled with a stream and ready to be read by the SW, the size of this stream (number of bytes) is sent by the FPGA using a WireOut, and a Trigger is activated, to notify the SW that the function ReadFromPipeOut can be called.
The FIFOs use two clocks : sys_clkp (the oscillator on the board) for the WR port, and okClk for the RD port.
See the relevant part of the VHDL code (process synchronized on okClk) :
[CODE]PipeInterface : process(Reset, okClk)
if (Reset = ‘1’) then
FifoFlushState ‘0’); – used to notify the SW that a stream is ready
ep20wire ‘0’); – used to send to the SW the size of this stream
elsif rising_edge(okClk) then case FifoFlushState is when FIFO_RESET_ST => FifoFlushState if (Stream0Ready = '1') then FifoFlushState ep60triggerOut if (Stream0Ready = '1') then FifoFlushState end case; end if;
On the SW side, functions are called this way (I’m really not a C++ programmer so this may not be standard syntax…) :
long flag = 0;
while (flag != 1)
flag = dev->IsTriggered(0x60, 0x00000001);
iCurrentStreamSize = dev->GetWireOutValue(0x20) + 8; // FPGA sends on this wire the size of the next stream
ret2 = dev->ReadFromPipeOut(0xA0, iCurrentStreamSize, pBuffer);[/CODE]
I run tests where 25 streams with increasing size (from 176 to 3672 bytes) are generated and sent through the PipeOut.
The thing is, sometimes it works fine (the 25 stream sizes are correct, and when I display the data I can see that it is correct), sometimes the value on the WireOut does not update, or is totally wrong. Is there something fundamentaly wrong in my implementation ? Should I give more time to the WireOut so that it updates correctly ?
Thanks in advance for your answers.