Hi,
I would like to verify the timing of the SDRAM interface using a scope and or logic analyzer. I have started scratching away the solder mask of some vias trying to find the relevant signals. As you can imagine this is very time consuming. It would be REALLY nice if you could publish a drawing with all the vias marked that carry any of the signals to and from the SDRAM that are accessible from the back, i.e. when the board is plugged in.
Thanks, Klaus
Klaus–
Have you tried using Xilinx ChipScope? It is a much more useful tool than a logic analyzer and allows greater flexibility from it’s “inside the FPGA” perspective.
Timing closure is typically accomplished by using the Xilinx timing tools as well as the published setup/hold times for the SDRAM. Xilinx provides extensive tables that show the I/O timings under different circumstances.
The SDRAM interface works fine, but I need to know what my margins are.
My client insists on measurements. Calculations based on data sheet parameters and tables won’t make them happy, I’m afraid.
Klaus
Klaus–
If you have one or two pins you’d like help finding, I may be able to oblige. Unfortunately, we just cannot provide Gerbers or similar images.
Please send directly to [email protected]
I need help to make my thesis, because I take days working in a DDR SDRAM controller of a Spartan 3E and I have many doubts. Please if he/she can you help me.
My English is not good. I’sorry