In the XEM8350 power distribution block diagram, there are 4 voltages sent to the mezzanine connector pins.
3.3V, 1.8V, VIO1 and VIO2
VIO1 and VIO2 are generated by a Texas Instruments TPS65400
This chip has 4 buck converters (two capable of 4 A and two capable of 2 A). I understand that the details of how the FPGA gets power isn’t relevant for end users. It would be very helpful for users to know how the VIO1 and VIO2 pins are connected to their regulator when using the VIO pins at MC1-147, MC1-176 and MC2-2, MC2-4 to power external devices…such as level translators.
If these voltage rails are duplicates of the I/O bank voltages, does that mean they can provide the full 2A each on the mezzanine connector pins?
If these voltage rails are directly powering the FPGA I/O banks, does this mean the mezzanine connector pins can provide only whatever available power is left after powering the VCCO banks?