Xilinx can generate structural netlist VHDL at several points in the tool chain, including after synthesis, after mapping, after translation, and after place-and-route.
I’m having no trouble simulating the last three (other than speed using Modelsim PE.
However, in attempting to simulate with a post-synthesis VHDL netlist (produced in the netgen/synthesis directory by default), the simulator can’t bind the okHostinterfaceCore component. I assume this is because the provided simulation libraries only have an okhostinterface component and not a separate “core” component (at least judging by the directories in the sim libraries)? The other entities like okWireIn, etc. are apparently not a problem.
Is there a way to simulate the post-synthesis files? It would be nice because it looks like these are the smallest netlist files and would probably run faster than the post-PAR version, for example.