Post routing simulation


I’ve been trying to perform a post a post place&route simulation (I’ve done a behavior simulation and it worked well). I’ve been using the procedures from OpalKelly (FrontPanelReset, SetWireInValue, …) to simulate in modelsim XE III starter 6.3c.

It looks like it keeps waiting for the hi_out(0) goes down in the FrontPanelReset procedure. Here it is how the procedure looks like after some debugging code:

[CODE] -----------------------------------------------------------------------
– FrontPanelReset

procedure FrontPanelReset is
variable i: integer := 0;
variable msg_line : LINE; – type defined in textio.vhd
for i in 31 downto 0 loop
WireIns(i) := (others => ‘0’);
WireOuts(i) := (others => ‘0’);
Triggered(i) := (others => ‘0’);
end loop;

  write(msg_line, STRING'("Reseting FP - setting DReset")); writeline(output, msg_line);
  wait until (rising_edge(hi_in(0))); hi_in(7 downto 4)  commands with hi_in operator work fine but the one with the hi_out is not.

Again, the same code works fine for behavior simulation.

Any suggestions would be greatly appreciated.

Luiz Gouveia


The simulation libraries we provide are for behavioral sim only. They do not support post place & route simulation.

Is there a plan to provide libraries for back-annotated simulations?

I am also having difficulties in debugging without the ability to run netlist level sims.