PLL source options DIV1CLK/n and DIV2CLK/n

FrontPanel
1

I attached a frequency counter to the clock 4, 5, and 6 outputs on the XEM3005 breakout board and experimented with the FrontPanel PLL control.

I observe the following with these source options.

DIV2CLK/2 only produces the frequency indicated by the application when DIV2N is a multiple of 4.
DIV2CLK/4 only produces the frequency indicated by the application when DIV2N is a multiple of 8.
DIV1CLK/2 only produces the frequency indicated by the application when DIV1N is a multiple of 4.
DIV1CLK/3 only produces the frequency indicated by the application when DIV1N is equal to 6 (and only 6).
DIV1CLK/3 produces what looks like DIV1CLK/4 when DIV1N is a multiple of 8.

The frequencies shown by FrontPanel don’t change when DIV1N or DIV2N are changed and the above source options are used. The display is simply the REF or VCO frequency divided by 2, 3, or 4, as the case may be. But the frequency counter reports changes when DIV1N or DIV2N are changed. My observations seem to line up with a section of the Cypress document for the CY22150.

When DIV1N is divisible by four, then CLKSRC(0,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1).
When DIV1N is six, then CLKSRC(0,1,1) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0).
When DIV2N is divisible by eight, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0).

Perhaps the FrontPanel application could indicate N/A when these source options are chosen and the DIV1N or DIV2N values don’t meet these constraints.

2

Yes, as you say, the constraints are provided in the Cypress manual. FrontPanel has very limited business logic to prevent incorrect settings.

3

OK. If the FrontPanel application cannot address this, perhaps the user manual could include some words to the effect that “restrictions apply to the divider values DIV1N and DIV2N when the source DIV1CLK/n or DIV2CLK/n is used. See the data sheets for the PLL.” Otherwise, people like me will look at the GUI and the appropriate section of the manual and wonder why they are not seeing the frequencies that they are told to expect on the output pins.

In addition, the FrontPanel user manual includes a table of “Example PLL Configurations” and the table includes “N/A” for the DIV1N and DIV2N values for the examples with DIV1CLK/3 and DIV2CLK/4. That is wrong because these values do affect the actual generated frequency when they do not meet certain constraints.