Plea for halp


Why this project does not work?
After several moth of not doing anything on XEM3001 I am starting to use it to transfer data between the XEM3001v1 and a host PC. Then nothing works and I don’t understand what is the problem.
In my project I try to use pipeIn and pipeOut to move data between the FPGA - dual port ram and the host PC and I can’t get back what I send. Maybe someone see obvious mistakes that I make or there is a update that I did not install correctly
I am using XEM3001v1 and API - VC++ compiled on microsoft VC6. (i did load the most recent updates from OK website)
Attached are the HDL and CPP projects. It is as simple as I could make it but it dont work
Than for your help
Ehud (0 Bytes) (0 Bytes)


Hi Ehud-

It’s good to hear from you again. Can you tell me what version of firmware you’re using right now? Using FrontPanel, you can click “FrontPanel->Set Device ID” and it will display the firmware rev.

Are PipeIns (to the FPGA) working properly? You can replicate the read/write signals from the PipeOut / PipeIn to general I/O pins. Then using an oscilloscope, are those pins being strobed?

I would start with the DES application to see if that is working (use the precompiled stuff initially). If that works, you can try building it yourself in VC6 to test your libraries and build procedure.

You could also test PipeIn functionality independently by sending pipe data to the LEDs.



I’ve only briefly looked at your code (not compiled it or anything). However, in your mem_addra.v file, you seem to be creating address counters for reads/writes, correct? These counters feed the address (port A) for the dual-port memory.

I think you may be making the mistaken assumption that, during a read or write operation, the read (or write) signal remains high for the entire period. That’s why you use “pipe80Iwrite” as the select for the address counter. It’s also why you’re resetting the counters when (~pipeAO0read) or (~pipe80Iwrite).

When a write (from a PipeIn) occurs, the write signal is asserted for one TI_CLK. While the spec allows for write to be asserted for consecutive TI_CLKs, this is not necessarily the case. In other words, writing 10 words may take many more than 10 clock cycles – with write becoming deasserted after each individual write.

Does this make sense? Is this perhaps the cause of your problem?


Yes! You are correct. I assume that the pipe80Iwrite is continuously active (high) while data are moved from the buffer on the PC host through the usb to the fpga. In fact, I did look on this signal and it was intermittently hi but most of the time low (as far as I remember), at that point I realized that I am missing something important and I decided to post the request for help. I have never seen timing diagram of the of the pipes operation.
I also tried to use conditional assignment to take control of the address bus (addra) but it never worked.
I is still not clear to me how exactly to write/read to this dp ram using ok pipes.
Your DES application works perfectly but I still don’t understand how to fix my application which is even simpler, I guess I need to study it more carefully.
I have Opal Kelly board XEM3001, firmware version 1.3 and serial number vozukyHYKi.
Thanks for your prompt reply



The Pipes have been designed to be compatible with the way the Xilinx dual-port memories operate. You should be able to wire them up with very little logic.

For example: Connect the PipeIn EP_WRITE signal to the RAM Write Enable signal (and address increment). Then connect the PipeOut EP_READ signal to the RAM Read signal (and address increment).

Since your DP RAM has both input and output data busses for each port, you can connect the PipeIn to the input data bus and PipeOut to the output databus.

You can see PipeIn and PipeOut timings in the FrontPanel User’s Manual on pages 27/28 of the most recent revision.