The “black boxes” for both the VHDL and Verilog projects are provided in the precompiled .ngc files in the \FrontPanelHDL\Xilinx* directory. The ISE 7.1 .ngc files work with 8.1.
To compile with them, first you have to create a new project directory (the given Samples directory doesn’t work because Xilinx ISE project directories can’t have a space in the path).
Next, you need to copy the pipetest.vhd, pipetest.ise, and *.ucf file to the new project directory. Then, copy the okLibrary.vhd and all the .ngc files from the \FrontPanelHDL\XilinxISE71_v2 to the project directory as well.
Opening up the pipetest.ise file, you may have to auto-update the project (if using ISE 8.1) and then add the okLibrary.vhd file back to the project.
Generate the .bit file and you’re done. So, basically for any FrontPanel project, you need the .ngc files, either okLibrary.v or okLibrary.vhd, and a .ucf file with at least the necessary connections between the FPGA and USB controller.
The buffered pipes are created using an okPipe and a fifo. The fifo used is detailed in the Xilinx application note 131. I believe it uses two block RAMs per buffered pipe.
If you require more control and/or performance from your piped data than is offered by the buffered pipes, you could create your own by using a standard okPipe module with a Xilinx FIFO core (which is now free in ISE 8.1 Webpack!).