PipeOut and WireIn work, but PipeIn times out

FrontPanel
1

I have a XEM3001v2 board. While WireIn and PipeOut are working on this system, PipeIn does not seem to work and instead it just stalls. By checking the error code I can tell that this is a timeout but I’m not sure why it would happen this way. Is this related to Windows7’s restrictions? But then how come WireIn can work?

EDIT: The problem is fixed now, it was a stupid mistake on my part.

2

Please try our samples. Do they work? DESTester and PipeTest both use pipes.

3

I tried DEStester and it works. I actually copied most of my own code from it.

Also I checked the ep_write signal coming out of the PipeIn module, but it stays low throughout the transfer. Which means that somehow that the pipe is not even being activated, perhaps.

4

Step by step from DESTester, at which point do things break?

5

I use DEStester.cpp’s InitializeFPGA function (except the configuration part). For the write to pipe this is my function

void WritePatternMem(okCFrontPanel *xem, char* filename)
  {
  ifstream pfile;
  string line;
  unsigned char buf[6000]; // 3000 entries x 9 bits each.
  int bufcounter = 0;

  pfile.open(filename, ios::in);
  if(pfile.is_open())
    {
    while ( pfile.good() )
      {
      int temp = 0;
      getline(pfile,line);
      for(unsigned int i=0; i < line.length(); i++)
        {
        int b = (line* == '1')? 1:0;
        temp = temp + b*pow(2,8-i);
        }
      // byte order was checked with hex editor. Not sure if this is the right one for OK
      buf[bufcounter++] = temp&0x00FF;      // MSB in lower address
      buf[bufcounter++] = (temp&0xFF00)>>8; // LSB in upper address
      printf("%d \n", temp);
      if(bufcounter == 6000)
        break;
      }
    }
  pfile.close();

  // wire. this is used to prep FPGA for transfer
  if(xem->SetWireInValue(0x08, 0x01, 0x01) < 0)
    printf("Some Error in Wire In\n");
  xem->UpdateWireIns();
  
  xem->EnableAsynchronousTransfers(true);

  int ret;
  if( (ret = xem->WriteToPipeIn(0x80, 512 , buf)) < 0)
    {
    printf("Cannot write to pipe 0x80\n");
    if(ret == okCFrontPanel::InvalidEndpoint)
      printf("Invalid Endpoint\n");
    if(ret == okCFrontPanel::Failed)
      printf("Failed\n");
    if(ret == okCFrontPanel::Timeout)
      printf("Timeout\n");
    }

  if(xem->SetWireInValue(0x08, 0x00, 0x01) < 0)
    printf("Some Error in Wire In\n");
  xem->UpdateWireIns();
  }

The wires seem to be updating just fine. I’ve set an LED to show the status of ep_write on the pipeIn module in the FPGA. But that LED never changes. Even while this code is stuck in the transfer function. After a while it just gives up and returns an error. I tried changing the address of the endpoint to make them unmatched, but it still gives me the same error - timeout - not that the address is invalid.

EDIT: I should add that in simulation using the provided HostCalls, the verilog works just as expected.

EDIT: As suggested here
http://wiki.opalkelly.com/troubleshooting
I tried disabling (and enabling) asynchronous transfers, but the same results.

EDIT: Ok I fixed it :stuck_out_tongue: I had not connected the ok2 port to the PipeIn module in verilog. I feel sheepish now!*