I set up a simple 16-bit wide, 16 word deep FIFO using the Xilinx IP. I am able to monitor the addition of data as I add it to the FIFO using PipeIn. However when I try and read either of the first two words I get 0s regardless of what I put in the FIFO. I’m using the Python API.
That is, if I do the following:
buf = ‘\x04\x05’
read = ‘\x11’ (something arbitrary and nonzero to be able to distinguish)
I get read = ‘\x00\x00’ or for map(ord,read) I get [0,0].
Now, if I write in 16 words to fill up the FIFO and then read it out, the output of map(ord,read) is
[0, 0, 0, 0, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5]
where the first four 8-bit words shouldn’t be zero.
I think this is a timing issue that I’m not seeing, specifically with timing the readout. It says in the FrontPanel UM that when EP_READ is asserted on the rising clock edge of TI_CLK the HDL must respond with EP_DATAIN on the next clock edge. I think my problem is that I’m not timing the read out right. Specifically, it seems to be missing data for 2 clock cycles, since it misses the first two 16-bit words.
Any help is appreciated. I’ve attached the verilog code.
led.v.zip (1223 Bytes)