PipeIn Timeout C++

I am observing some strange behavior related to timeouts with PipeIn with a terminal interface that I’m writing to control an XEM6010.

Specifically, I have a menu where a user chooses from a number of options, one of which is to transfer 2 bytes to a 16 bit wide register in the FPGA. If I choose this option, it will successfully transfer the two bytes as many times as I select that option until I close the program. After closing the program, if I reopen it and try to transfer the two bytes again, I get a Timeout error code (-2).

I discovered that the only way to transfer the 2 bytes again is to run the RAMtester example and then reopen my program. After running RAMtester and then running my program, I can again transfer the 2 bytes repeatedly to the device over the PipeIn until I close the program.

I am currently terminating the program with the following lines:

xem->SetWireInValue(0x00,0x0000,0x00FF); xem->UpdateWireIns(); cout << endl; cout << "Shutting Down..." << endl; cout << endl; delete xem; exit(0);
I looked through the examples and API but didn’t see anything obvious about closing connections. Is there a recommended way to disconnect in order to avoid this? Does anyone have suggestions for tracking this down?


If I disconnect the USB and power, the PipeIn will not work until I run RAMtester. This makes me believe that there could be some initialization that is required that I must be missing. Here is a list of calls I’m making through the DLL during initialization.

*]okFrontPanelDLL_GetVersion(dll_date, dll_time);
*]okCFrontPanel *xem = new okCFrontPanel;
*]int numDev = xem->GetDeviceCount();
*]serialNum = xem->GetDeviceListSerial(0)
*]configErr = xem->ConfigureFPGA("./xilinx/control.bit",configDownloadStatus,test);

Have I missed an initialization that would affect the PipeIn only? WireIn works.


It looks like this is actually a problem in my verilog somewhere. I copied the ramtest.v file and stripped out everything but the okHost and one pipe. After doing this I was able to repeatedly send data to the FPGA through the PipeIn function. I’ll have to piece my verilog back together and see where exactly it went wrong.