I’m trying to wire up a PipeIn module to a dual port fifo, and a PipeOut module to another dual port fifo.
For the PipeIn module, I have the ti_clk connected to the wr_clk port on the fifo. I was wondering if I should connect to the hi_clk at the top_level.
Also, what is the difference between hi_clk and ti_clk?
Thanks in advance.