PipeIn/PipeOut fifo clocks


I’m trying to wire up a PipeIn module to a dual port fifo, and a PipeOut module to another dual port fifo.

For the PipeIn module, I have the ti_clk connected to the wr_clk port on the fifo. I was wondering if I should connect to the hi_clk at the top_level.

Also, what is the difference between hi_clk and ti_clk?

Thanks in advance.


Hi comxander-

TI_CLK and HI_CLK are currently identical. However, you should use TI_CLK since that is technically the ‘target-interface’ clock. While unlikely, it is possible that we would change the relationship between TI_CLK and HI_CLK in a future revision.