Pipe cores instantiation in verilog

Hi, I noticed the an inconsistency in the signal orders of pipe HDL core instantiations between what listed in FrontFpanel User’s Manual and that listed in okLibrary.v . For example; For okPipeIn,
in FP user’s manual, the usage is
okPipeIn pipeIn9C (ok1 => ok1, ok2 => ok2, .ep_addr(8?h9c), .ep_dataout(ep9Cpipe), .ep_write(ep9Cwrite));
while in okLibrary.v, it is
okPipeIn(ok1, ok2, ep_addr, ep_write, ep_dataout);
Notice the reversed order of the signal ep_write and ep_dataout between the two. The of version of my FrontPanel is 3.0.10, and I believe the signal order in okLibrary.v is correct, and the manual is wrong. I guess I could confirm that by compiling and an example, but it might be even easier by posting a the question here. Thanks

Order does not matter if you explicitly call out the mapping.

Thank you. I should have known that.