Pinout of BRK3010


#1

Do you have a pinout table for the BRK3010? I’m looking for a table that maps pins on the FPGA to pins on JP1, JP2, JP3 and JP4 of the breakout board.

The diagram in the XEM3010-UM is unreadable.


#2

Hello-

Perhaps we should be more explicit on this. The pins are mapped, in order, according to their location on the XEM3010.

So:
JP1-1(BRK) --> JP2-1(XEM)
JP1-2(BRK) --> JP2-2(XEM)

JP1-40(BRK) --> JP2-40(XEM)
JP2-1(BRK) --> JP2-41(XEM)

JP2-40(BRK) --> JP2-80(XEM)

The other two connectors on the BRK (JP3, JP4) are wired similarly to XEM JP3.

Due to the way the 3D model is rendered to PDF, it is a bit difficult to read unless you zoom in. The actual silkscreen on the BRK3010 is much easier to read.

The breakout board for an upcoming product uses a different approach – the silkscreen is labeled with the JP pins from the XEM itself. Would you consider this to be a more usable style?


#3

Yes, it would help if you were explicit on this. It might be reasonable for me to assume such a mapping, but I’m left to guess and then I have to test my assumption by reverse engineering the BRK3010.

When I zoom in to the PDF drawing, the text stays unreadable. See the attached jpg, this is a screen capture at 1600x zoom.

The actual silkscreen on the BRK3010 is much easier to read.

Not if you are over 40. :slight_smile:

… silkscreen is labeled with the JP pins from the XEM itself … a more usable style?

I’m not sure I understand. Does that mean JP1-6(brk) will be labeled JP2-6(XEM) instead of JTAG_TCK? That would be confusing. I like the way the breakout board is currently labeled - I just wanted it in a PDF file so that I don’t have to carry a breakout board around to determine the mapping while I’m designing. In the lab we’ll want the breakout board labeled as is so that we can attach probes for ad-hoc tests.


BRK3010_zoom.JPG (10.8 KB)


#4

Yes, the PDF for the BRK doesn’t hold up to zooming nearly as well as the XEM one. We’ll look into that.

We would maintain the names for things like VCC, JTAG_XXX, and so on. But the names like XBUS would go away. Here’s the reasoning:

The only names that have much relevance are the FPGA pin (e.g., B16) and the XEM connector pin (e.g., JP3-17). The XBUS names have no relevance because in almost any user design, these names aren’t present. Instead, you have SDRAM_D13, and ADC_CLK, and so on. Of course, we cannot put these names on the BRK board, so we’re left with the other two options.

The FPGA pins are fairly meaningful. However, their are not consecutive and therefore are more difficult to work around for bus names. For example, if you had assigned a bus XD[0…15] to connector pins JP3-5…JP3-20, it is easier to follow the sequence on the connector pin than to follow the non-patterned FPGA pin.

We have also started to put comment fiels in our template UCF files that contain the connector pin names (JP3-5). Therefore, you have a line-by-line correlation between the FPGA pin and the connector pin. You’ll also have, in that same file, your design pin name, so everything is nicely present in a single file.

Does this make sense?


#5

Does this make sense?

I think so. You plan to label JP2-17 JP2-47.

Personally, I prefer the less ambiguous logical labels you are currently using. But it is a minor issue.

(BTW, thanks for the clarification on the pinouts.)


#6

More important … do you plan to have a proto region on the new breakout board? That would be very nice.


#7

[QUOTE=Opal Kelly Support;1117]

Perhaps we should be more explicit on this. The pins
are mapped, in order, according to their location on
the XEM3010.

So:
JP1-1(BRK) --> JP2-1(XEM)
JP1-2(BRK) --> JP2-2(XEM)

JP1-40(BRK) --> JP2-40(XEM)
JP2-1(BRK) --> JP2-41(XEM)

JP2-40(BRK) --> JP2-80(XEM)

The other two connectors on the BRK (JP3, JP4)
are wired similarly to XEM JP3.

Just a quick confirmation, to prevent problems in case this is taken literally, the pin numberings given above are transposed from one side of the connector to the other.
eg. they should be:

JP1-1(BRK) --> JP2-2(XEM)
JP1-2(BRK) --> JP2-1(XEM)

JP1-39(BRK) --> JP2-40(XEM)
JP1-40(BRK) --> JP2-39(XEM)
JP2-1(BRK) --> JP2-42(XEM)
JP2-2(BRK) --> JP2-41(XEM)

JP2-39(BRK) --> JP2-80(XEM)
JP2-40(BRK) --> JP2-79(XEM)

This is according to the data given on pages 23-25 of XEM3010-um.pdf and referencing the silkscreen printing on the BRK3010 board.

Cheers.


#8

— Begin quote from gstewart;1121

More important … do you plan to have a proto region on the new breakout board? That would be very nice.

— End quote

How would you arrange a prototype area? Would it just be a grid of 100 mil holes with no +3.3V or DGND strips?

If we need to attach something to a BRK, we “dead bug” the device. Since most people use surface mount devices and it’s difficult to make a easily configurable “grid” of pads for random through-hole parts, we were at a loss.

If you have a good idea of how the prototype area would look, let us know and we’ll consider it for future boards.

Thanks,
Garrick


#9

— Begin quote from Fibics;1235

Just a quick confirmation, to prevent problems in case this is taken literally, the pin numberings given above are transposed from one side of the connector to the other…
This is according to the data given on pages 23-25 of XEM3010-um.pdf and referencing the silkscreen printing on the BRK3010 board.

— End quote

This is correct. Perhaps we should be more verbose in our listing of the signals, but we assumed users would simply reference the PCB.

Garrick