Pin confusion

From the xem5010.ucf file:
NET “xbusp” LOC = “G25”; # JP2_9 ****
NET “xbusn” LOC = “G24”; # JP2_11 ****
NET “xbusp” LOC = “J26”; # JP2_10 ****
NET “xbusn” LOC = “J25”; # JP2_12 ****

From the User’s Manual:
9 G24 L3P_SM5P_13
11 G25 L3N_SM5N_13
10 J25 L4P_13
12 J26 L4N_VREF_13

So which FPGA connector corresponds to which JP2 pin? My assumption is that it’s the comments in the ucf-file that is wrong, but why has p/n of the xbus been switched and why has these lines been marked by “****”?


The User’s Manual is correct. The UCF file should read:

#NET "xbusp" LOC = "G24"; # JP2_9 #NET "xbusn" LOC = "G25"; # JP2_11 #NET "xbusp" LOC = "J25"; # JP2_10 #NET "xbusn" LOC = "J26"; # JP2_12

The prototypes of our XEM5010 had these pin polarities swapped. In production the pins were mapped as the User’s Manual says. The UCF file got a late update. The asterisks were used to mark those for change.

User’s Manual :

xem5010.ucf :
NET “ssram_a” LOC=“N23” | IOSTANDARD=“LVCMOS18”;
NET “ssram_a” LOC=“L23” | IOSTANDARD=“LVCMOS18”;
NET “ssram_a” LOC=“K23” | IOSTANDARD=“LVCMOS18”;
NET “ssram_a” LOC=“H23” | IOSTANDARD=“LVCMOS18”;
NET “ssram_a” LOC=“P23” | IOSTANDARD=“LVCMOS18”;

According to test result xem5010.ucf is correct

Yes, the UCF is correct and this is reflected in an updated XEM5010 User’s Manual posted to our website recently.