okRegisterBridge operation

I’m confused about the direction of some of the signals in okRegisterBridge (FrontPanel 4.2.5).

I thought the way this works is that I issue a command on the PC to either read or write one or more registers, and the okRegisterBridge asserts ep_address and ep_write or ep_read, and my HDL responds to those read or write commands (and my HDL maintains any actual registers).

However, in the FrontPanel VHDL package okRegisterBridge has ep_address and ep_read as inputs. In the manual ep_write is also listed as an input (it’s an output in the HDL).

Should all three of ep_address, ep_write, and ep_read really be outputs? Can I make this work just by editing the FrontPanel package definition for okRegisterBridge? Have I completely misunderstood how this is supposed to work?

Furthermore, ReadRegister and the other Register Bridge commands are missing from the online API docs (
). I can probably figure out how to use them from the metadata in Visual Studio.

The description of the okRegisterBridge is correct in text in the FrontPanel User’s Manual. The table with the directions is incorrect and will be updated. The only input to the okRegisterBridge is EP_DATAIN.

Yes, the VHDL package was incorrect. That has been updated since 4.2.5 was released, and will be in the next release. If you need something sooner, contact support@opalkelly.com