Hello,
I am using the Register Bridge on an Opal Kelly FPGA, and I have a question regarding the behavior of the regRead signal during waveform verification through Host Simulation HDL.
Context:
- Currently, I am using the
ReadRegisterSettask from theokHostCalls.vhfile. - I have created custom register arrays to store the desired Address and DataIn values, which are used as
shown in the attached code.
OK_TOP_tf.v
> reg [31:0] RegInData_MonData [0:(`num_neurons+`num_neurons*`len_synmap-1)];
> reg [31:0] RegAddresses_MonData [0:(`num_neurons+`num_neurons*`len_synmap-1)];
> reg [31:0] Size_RegMonData;
>
> initial begin
> for (i=0; i<(`num_neurons+`num_neurons*`len_synmap); i=i+1) begin
> RegInData_MonData[i] = 32'h0000_0000;
> RegAddresses_MonData[i] = 32'h0000_0000;
> end
> Size_RegMonData = `num_neurons+`num_neurons*`len_synmap;
> end
>
> task Monitored_Data_Reg_Bridge ();
> begin
> for(i=0; i<(`num_neurons+`num_neurons*`len_synmap); i=i+1) begin
> RegAddresses_MonData[i] = (i+1) << 12;
> end
> ReadRegisterSet_MonData_User;
> $display("Read from Monitored data register array: ");
> $display("--------------------------------------------------");
> end
> endtask
okHostCalls.vh
> task ReadRegisterSet_MonData_User ();
> integer i;
> begin
> @(posedge hi_clk) hi_cmd[2:0] = `DRegisters;
> @(posedge hi_clk) hi_cmd[2:0] = `DReadRegisterSet;
> @(posedge hi_clk);
> hi_drive = 1;
> hi_cmd[2:0] = `DNOP;
> @(posedge hi_clk); hi_dataout = Size_RegMonData;
> for (i=0; i < Size_RegMonData; i=i+1) begin
> @(posedge hi_clk) hi_dataout = RegAddresses_MonData[i];
> @(posedge hi_clk); hi_drive = 0;
> @(posedge hi_clk);
> @(posedge hi_clk) RegInData_MonData[i] = hi_datain;
> hi_drive = 1;
> end
> wait (hi_busy == 0);
> end
> endtask
Problem:
From the User Manual, I understand that the regRead signal can assert continuously over consecutive cycles of okClk.
However, after verifying the waveform in Host Simulation HDL, I noticed that the regRead signal asserts only once every 5 cycles of okClk. (Unfortunately, I can’t upload the images because I’m new user)
Due to this, the data reception rate is lower than expected, and I am looking for a way to configure the design so that the regRead signal asserts continuously over consecutive okClk cycles.
Questions:
- Is there a way to ensure that the
regReadsignal asserts continuously over consecutiveokClkcycles by modifying theReadRegisterSettask or other parts of the design? - If there are specific configurations or HDL adjustments required, I would appreciate your guidance.