Hi,
I’m a beginner with frontpanal and recently I’m learning it by writing a ram in the FPGA. Actually, the ram works well and the size is 16bit * 1024. Now I want to read the data out to my GUI from that ram by pipe transferring. But I have no idea how to do it with okpipeout, including the port map and the GUI program. Can someone give me some hint about it or give me a demo which can do the same work?
I’m using XEM6010-LX150, coding with VHDL and C#.
Thank you!
The port map is in the FrontPanel SDK documentation online, as is the component definition for the GUI. For examples of pipe examples in C# and VHDL, please see the samples included with the FrontPanel SDK. Namely PipeTest (not just a clever name!) and DESTester.
I have just finished a project using C# and an XEM7001 using okBTPipeOut under Verilog (I’m a beginner at both). I based mine on the the PipeTest and DESTester samples as mentioned above. If they don’t give sufficient guidance, can you provide more detail on where you are getting stuck?
Hi, thank you very much for your reply. I would like to use the okBTPipeOut to transfer the data in my block ram to my GUI. The example given in the PipeTest is to transfer the pseudorandom data rather than the data in the ram. My ram is 5000000 * 1bit large and it outputs the corresponding data when the address is given. I wonder how I can connect the PipeOut entity to the ram and how to fulfill the timing diagram.
Thank you very much for your help!
Regrettably, I used a FIFO in the FPGA, as my board does not have RAM, so I don’t know how to connect RAM to the pipe. Is the RAM set up as a FIFO? If not, then I imagine you would want to construct a FIFO in the FPGA to buffer the data. At that point the example would give guidance or I could help more.