okCLK Host interface clock mystery

Hi, since everything about Frontpanel needs to be proprietary for some reason, (not even a schematic?) it seems that it also needs to be very well documented. I can’t find anything about the “Host Interface Clock” can someone tell me where the okClk from the Host IP (FrontPanel Subsystem) comes from, what is the clock tree how is it generated does it go through clock buffers, MCMs, PLLs, what is the source on the XEM7310T board?

If it is the 200MHz off chip oscillator, is the LVDS receiver embedded in the proprietary ohHost IP, meaning the raw clock cannot be used elsewhere in the design? All I can find about it in the documentation is that it is 100.8MHz. Where does that number come from and why not 100M? Apparently not a /2 OF THE 200MHz. So what is the source, what are the specs of the source? Stability, jitter, accuracy etc. Thank you, this information is essential to any kind of useful User RTL and timing constraints.

The 100.8 MHz clock for the host interface is not specified or guaranteed to any particular level of accuracy, jitter, etc. We typically select a 50 ppm source for this task.

We provide constraints in our HDL for this oscillator to meet the timing required by our host interface.

If you require additional levels of accuracy or performance (as may certainly be the case for some applications), we suggest using something selected for your application and provide appropriate clock domain crossing logic to assure reliable communication with the host interface.

Ok thank you, I did end up using the 200MHz external oscillator to get the performance I needed for an AXI clock, but would still appreciate more information about the host clock, as being synchronous to it is an advantage in some parts of the design without worrying about domain crossing and timing issues…

Can you share what the source of the host clock looks like? Is it an on board oscillator, where does it come from, (how is it generated) what MMCMs does it go through, ,what clock buffers to get some idea how it routes.? What is the source of this odd frequency clock? External oscillator, on chip clock? You speak of a 50ppm source, what is that source? Why the mystery?. Certain parameters, especially for clocks are needed to create a robust user design

All this unnecessary black box proprieterism works against the idea of incorporating OK IP in a final design, especially with the trend toward open source. Without sufficient information we aren’t able to properly review or document our designs, or predict and test behavior in some cases. We are at a decision point of using OK products, or rolling our own.

If not using OK IP there isn’t any point in using OP development boards. For any black box, specification of any signals exposed externally should be documented and complete. All you can give us is a frequency? If it is all so competition sensitive, can we sign a non-disclosure agreement to get basic info about the IP and the hardware (schematic) ?

There’s no secret or mystery about this clock. It’s a source of 19.2 MHz that is run through the Cypress FX3 microcontroller to drive their CPU and USB machinery. 100.8 MHz is simply the number that Cypress provides. You can review their documentation for additional information, if that’s helpful.

We’ve done our best to document the necessary and sufficient information needed to make informed engineering design decisions. The frequency is 100.8 MHz. The tolerance is 50ppm or better. If anything more specific is required, we advise bringing your own clock.

We’d be happy to discuss the advantages and disadvantages of choosing our products for your design but this technical support forum is not the best venue for that discussion. The decision likely comes down to your business requirements and, at least in our experience, not likely to depend on the PLL architecture used to create the 100.8 MHz host interface clock.

Please feel free to reach out to [email protected] to discuss further.