okBufferedPipeIn / okBufferedPipeOut problem



I’m using the XEM3010 with it’s SDRAM as a FIFO (among other tasks), receiving data from PC, and broadcasting it on several channels.

When I read a page of SDRAM data, I’ve noticed the following problem : the first sample I read in the SDRAM seems to be null, and the 2 last samples (510 & 511) seem to be identical.

To check this, I send data in SDRAM (with okBufferedPipeIn) and then I read it back (with okBufferedPipeOut).

The difference between my code and the RamTest project is that I change regularly the read/write SDRAM address, because of FIFO principle.

Notes :

  • I have the last release of VHDL code (October 2005),
  • the RamTest project works fine with my configuration (with the 2 modifications : use of Verilog version of SDRAM controller, instead of Vhdl version, and adjustment of refresh cycles to fit my SDRAM frequency : 60 MHz).

Is there any timing constraint or initialization to apply when setting read/write address of SDRAM ?

Or is there a Vhdl example of SDRAM access with regular changes of read/write address ?