I haven’t yet acquired an XEM3001 board, so forgive me for asking a question that may seem relatively simple.
I am developing a high-bandwidth data acquisition device (~26 to ~100 Mbps depending on what we can get), and I want to stream it in real time to the PC over USB2.
I see the HDL module “okBTPipeOut” which has a “ready” signal to indicate whether there is data ready to be sent over USB to the host. I was thinking I could use this to keep the FPGA from transmitting data when there is none to be transmitted.
I will be using the FrontPanel C++ API to acquire data from this board. From the FrontPanel documentation, it understand that if I call the ReadFromPipeOut() method and EP_READY is not asserted, the call may simply fail with a timeout. I assume this means that the pipe will be polled for some time to see if data becomes available.
Will I see a major performance drop if this method is used? If the FIFO is empty when I first call ReadFromPipeOut(), what is the polling period? Will it wait for only a few microseconds and check again, or will it wait for some number of milliseconds before checking EP_READY again? A millisecond may overflow my FIFO’s.
If I were to guess, I would guess that SetBTPipePollingInterval() sets the interval at which the pipe will be polled, and SetTimeout() sets the interval which would cause a timeout. But since SetBTPipePollingInterval() takes an argument in milliseconds, I think this may be too long.
Was the okBTPipeOut module designed to be used this way? Can I achieve a transfer rate of at least 100 Mbps while using it? Adding a large FIFO is an option but I would like to avoid it if possible.
Sorry if anything is obvious or unclear - I don’t have too much experience with the XEM3001 or USB transfers in general.