okBTPipeOut in fifo ADC transmission


I’m working with an 10 MSPS 12-bits Parallel output ADC and I’d like to use the internal ram blocks to form a FIFO, since usb reaches superior velocity. To do this task, I thinked about a 32 kB FIFO to compound a 512 kB (16 x 32 kB) window signal, performing a PipeOut read 16 times. However, I’d like to know how okBTPipeOut works - I mean, if it triggers automatically a PipeOut read or something like that to PC host - I couldnt follow EP_SIGNAL very well.

*I’d like to avoid the external ram usage for this job.

Thank you very much,


Please refer to the FrontPanel User’s Manual (page 39) for details on how Block Pipes operate.

In all communication, the FPGA is a slave to the host. The host initiates all transactions. Block Throttling may be used to adjust the speed of transmission without reverting to wires or triggers for handshaking. However, they sould NOT be used for long-duration throttling. It should be assumed that the data is available before the host starts the transaction.

You will have the best results if you use the onboard SDRAM. This type of application is precisely why the SDRAM is there. Our RAMTester sample is an excellent start to your project.

first of all, sorry for my english…
I’ve to solve a similar problem…
I’ve a 26bit ADC at 25Msps and I want to download the sample to the pc using the C++ API readformpipeout().
My problem is that the procedure of read is much slower than the write one.
I’m thinking to use a RAM (the onboard one or one create by me) to collect enought data, so that the time of writing is comparable with the reading one…
Can someone help me??