We use ncverilog for simulation, and I need to be able to simulate some basic wire, pipe, and trigger interactions. Initially we have been using some home-made rudimentary behavioral verilog to fill in the ok black boxes. However, now we need to run some back-annotated simulations, and since the black boxes are now filled in, I can no longer plug in this behavior code. Do you have any recommendations or documentation on how to stimulate the host interface?
Lane