Hi everyone.
I am new to Opal Kelly. I want to simulate the First.v file that is in samples. I didn’t change neither First.v nor First_tf.v. I copied .ngc files and okLibrary.v to project folder. I added these lines to modelsim.ini file
[SIZE=“1”]okFPsim_ver = C:/Program Files/Opal Kelly/FrontPanel/Simulation/ModelSimXE63c/okFPsim_ver
okFPsim = C:/Program Files/Opal Kelly/FrontPanel/Simulation/ModelSimXE63c/okFPsim[/SIZE]
at the end of verilog section. I copied the okHostCalls.v to project folder.
The problem is I cannot do simulations. When I start Modelsim from ISE, it loads the text fixture and necessary files without error. However the waves are not changing except for hi_in. It is changing from (10)2 to (11)2 constantly. Integer k is tied to 1024, data_out is tied to 0 and button is tied to (11)2. ic2_sda and ic2_scl are HighZ. All the others are not defined.
Any idea where the problem can be?
Note: I can succesfully generate First.bit file and it is correct.