Hi. I preface this feature request by admitting I have no idea how complicated it is to implement. I would like to be able to run simulations of entities which instantiate the hostinterface without having to comment out all code related to opal kelly components. Is there any way to provide libraries so that modelsim will not fail with messages like:
IMHO, to perform simulations with a design instantiating OK components, you have 3 possibilities :
1- write stubs for each OK component you are using (simulation of R/W transfers )
2 - If you use ISE , you can generate (non synthisable) VHDL from .ngc files (foreach ngc file : ngdbuild file.ngc ngd2vhdl $file.ngd)
3 - you can also perform back anotated simulations (in ISE, check the appropriate option ) after synthesis or P&R.
For solution 2 & 3, you need to know how exchanges are made between USB CTLER and FPGA
Solution 3 is really heavy (for each modification, you have to wait for ISE to regenerate )
Solution 1 is simple but cannot help you to fix possible problems due to integration (clock domains, data validity,etc…) .
Solution 2 is attractive but need to have some explanations on MCU FPGA links
Just to append to this thread for those searching around…
ModelSim libraries are now part of the FrontPanel 1.3.0 distribution. As of this writing, this version is in alpha with beta and release versions to follow relatively quickly.
The ModelSim libraries allow full host simulation capability – you can actually emulate the FrontPanel API calls that your application will make such as ActivateTriggerIn, ReadFromPipeOut, and so on.