MicroBlaze tutorial help?

Spartan-3 USB 2.0 Modules
1

I’m trying to run through the MicroBlaze tutorial, and I have a few issues stacked against me:

  • I know nothing about using MicroBlaze!
  • My EDK is 10.2 rather than 8.2
  • My hardware is XEM3005 rather than XEM3010

The first issue might be insurmountable, but I think the others are probably not a big deal.

In tutorial part I, step 1.V, I selected Spartan 3e, XC3S1200E, FT256, and I may have selected the 5ns speed grade (the options were 4 and 5, and I’m guessing this isn’t critical?). No issues that I’m aware of at this point.

The issue comes in at part I, step 2.II… I don’t have mp_opb bus available, and I can’t find a way to add it as instructed by the tutorial. I also don’t see anything related to DOPB or IOPB.

Can anyone offer me a pointer to move forward with? Should I post a screenshot to display exactly what I see in Platform Studio?

2

Working with MB is not a particularly trivial matter and I would encourage you to explore MB without any FrontPanel tie-ins first. Once you’re very familiar with the architecture, build procedure, and tool usage, then you would be in a better position to explore connecting it with FrontPanel.

Unfortunately, Xilinx has made changes to the bus architecture of MB since the tutorial was written, so much of it does not apply any longer. The general idea is still applicable and it can be used for further exploration.

But still, you should start with MB first and use whatever materials Xilinx now has available to explore.

3

It is possible to convert the okmicrointerface to be a PLB peripheral, but it is not trivial. I did it in ISE/EDK 9.2.

Study mg_ug.pdf, the ‘PLB v3.4 and OPB to PLB
v4.6 System and Core Migration User Guide’.
In short, you need to:
i) convert okmicrointerface to PLB
a) create a new PLB peripheral with sw reset, 26 registers and 18 interrupts
b) add ports ok1, ok2, ti_clk & led to okmicrointerface.vhd and the MPD file
c) copy the old user_logic.vhd over. Edit it (about 5 lines) per the migration guide.
ii) assign no driver for the okmicrointerface.
iii) edit sampleFunctions.c to set the interrupt vector by
adding ‘microblaze_register_handler(TestInterrupt, 0 );’ before the
mb_enable_interrupts() call.

good luck.
Richard

4

Hate to resurrect an old thread but I, too, am trying to migrate the OPB-based MicroBlaze project into a PLBv4.6 peripheral.

I followed Richard’s advice and read/followed the Xilinx migration doc. I believe I have completed steps i.a-c of his post.

Now I am trying to work through the Opal Kelly tutorial (
http://wiki.opalkelly.com/microblazev3
) with the migrated peripheral.
I believe I have completed Part I successfully.
In Part II, Step 5.III I attempt to Generate Programming File for the project. Here is where the process fails for me. NGCBUILD complains about two of the provided OpalKelly black box netlists, “okWireIn” and “okTriggerIn”. However, it does not complain about okWireOut, okTriggerOut, okBTPipeIn or okBTPipeOut.

Please see the ISE Console log below. What is different about the okWireIn and okTriggerIn that would fail in NGCBUILD? Has anyone been able to successfully integrate a PLB version of the OpalKelly MicroBlaze peripheral?

–paste begin–
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Reading NGO file
“U:/Xilinx/OpalKellyTest/source/okProcessor/implementation/plbv46_okmicroinferfa
ce_0_wrapper/plbv46_okmicroinferface_0_wrapper.ngc” …
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okWireIn.ngc”…
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn00” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn01” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn02” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn03” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn04” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn05” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn06” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okWireIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/wireIn07” (TYPE=“okWireIn”) because
one or more pins on the block, including pin “ok2”, were not found in the
file. Please make sure that all pins on the instantiated component match
pins in the lower-level design block (irrespective of case). If there are
bussed pins on this block, make sure that the upper-level and lower-level
netlists use the same bus-naming convention.
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okWireOut.ngc”…
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okTriggerIn.ngc”…
ERROR:NgdBuild:76 - File
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferface_0_wrapper/okTriggerIn.ngc” cannot be merged into block
“plbv46_okmicroinferface_0/USER_LOGIC_I/trigIn40” (TYPE=“okTriggerIn”)
because one or more pins on the block, including pin “ok2”, were not
found in the file. Please make sure that all pins on the instantiated
component match pins in the lower-level design block (irrespective of case).
If there are bussed pins on this block, make sure that the upper-level and
lower-level netlists use the same bus-naming convention.
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okTriggerOut.ngc”…
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okBTPipeIn.ngc”…
Loading design module
“U:\Xilinx\OpalKellyTest\source\okProcessor\implementation\plbv46_okmicroinferfa
ce_0_wrapper/okBTPipeOut.ngc”…

Partition Implementation Status

No Partitions were found in this design.

NGCBUILD Design Results Summary:
Number of errors: 9
Number of warnings: 0
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