One limiting factor is that the XEM is designed to abstract the USB interface from the user. In the interest of providing several available channels between the PC and the FPGA chip (called Pipes in our nomenclature), some speed hit is taken. i.e. there is some overhead involved.
USB itself is a shared bus, so much depends on what other devices are consuming bandwidth.
In dedicated, bursty transfers of moderate length (say a few seconds), I’ve seen pretty good rates. I have a system that integrates with Matlab and sends several channels of audio samples through the XEM and I can do better than real time in many cases. If your transfers start to tax the PC, though, transfers will slow down. An example is when there is other work being done on the PC and it starts to swap.
I have a firmware upgrade that should increase the read rate (FPGA to PC), but it isn’t available quite yet. It certainly won’t be any faster than the 12 MB/s. We are also planning another board that will include on-board RAM and higher transfer speeds – probably closer to the 20 MB/s range.
P.S. I missed your other post… The FIFO can do high transfer rates, but the question is – where does it get the data. The USB bus at full-tilt will only provide -half- that rate and that doesn’t include any of the USB overhead. So, you can expect high-speed bursty stuff for the length of the onchip (FX2) FIFOs, but that’s about it.
Regarding source code – we don’t provide the source code to the FX2 except under license. If you want licensing information, you can email email@example.com.
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