Hi,
I need a pointer in diagnosing a problem I have in using the IsTriggered function of the Matlab API. I built a data acquisition application with XEM3010. The FPGA on XEM controls a bunch of hi-speed ADCs on a carrier board. It works like this, each time when my Matlab application sends a trigger to start a data acquisition. Then the FPGA runs the ADCs, and deposit the data in buffers. It then send a ADC_done trigger to Matlab through a TriggerOut end-point. The matlab polls for the trigger using the function UpdateTriggerOut/IsTriggered. Upon detecting the ADC_done trigger, it will transfer the ADC data blocks back to my PC using BTpipeOut EP. It works fine, except I now noticed a problem. Once in a while (say a dozen such data acquisition cycles), the IsTriggered function keeps returning zero, like the FPGA has never triggered (which is almost impossible). I have spent a few days on this, trying to find what is causing the problem, but I am still clueless. So I would appreciate if someone could offer some suggestion. Thanks.
Hengjie
My suggestion would be to build in some debugging capability to make absolutely sure that the done trigger is being setup properly. Are you certain that the trigger clock (EP_CLK) is the same as the one generating the trigger signal?
The EP_CLK I am using is the 100MHz (?) clk1 from the on-board PLL as the way in the examples, while the clock that generates the ADC_done trigger is a 40MHz clock which I provide externally for my user logic. Are you saying I should also use the clk1 to generate the trigger ? Thanks.
_Hengjie
The EP_CLK needs to be the same clock as the one you’re generating the trigger signal with. So if the state machine that creates the ADC_done trigger is on CLKXXY, then you need to set EP_CLK to CLKXXY.
The whole point of the Trigger element is to synchronize to a clock domain. It cannot do this unless you give it the correct clock.
I have switched the ep clock to my user logic clock which receives TriggerIN and generates the TriggerOut signals. Now problem is gone, no more trigger skipping !! Thank you very much ! I am fine for now, and will be back with other problems :))
I need a very similar MATLAB code to write and read a FIFO inside the FPGA , I’m using the XEM 3010-1500
Is it possible for mahengjie to post the setup need in MATLAB?
How can I can contact mahengjie? by email or wait for reply?
This is an old thread.
Thanks
Just saw this. Don’t know if you are still looking for the info. I will post something for you tomorrow.
— Begin quote from mahengjie;2351
I have switched the ep clock to my user logic clock which receives TriggerIN and generates the TriggerOut signals. Now problem is gone, no more trigger skipping !! Thank you very much ! I am fine for now, and will be back with other problems :))
— End quote
I have tried for half a moth with matlab communication with FPGA through API communication.
I don’t know how to set up the environment.
Can someone post a sample code?
Thanks very much.
Have you contacted the folks at Mathworks?
Matlab is their product and has an external interface that is designed to work with 3rd-party DLLs.
Hi Administrator,
which is the DLL file that I should use?
After I installed the Front Panel, I can not find the proper .dll file under matlab folder.
Can you help me with that?
Or can you post a executable sample, I tried each sample, not work.
Thanks very much.
Our installer only installs one DLL. Please have a read through our FrontPanel User’s Manual and I think many things will become clear.