I am a total newbie to LVDS.
I have no idea on how to use LVDS with the XEM3010.
I have tried several examples on the web, only to have all of them fail.
I’m not sure if I am supposed to add something to the constraints file?
I have read about the voltages, but all I am doing at this point is compiling.
Thanks,
Here is just a sample of the errors I am getting.
NET “data_out_P” LOC = “D1” | IOSTANDARD = LVDSEXT_25; #“ybus”
NET “data_out_N” LOC = “D2” | IOSTANDARD = LVDSEXT_25; #“ybus”
U1: OBUFDS
port map (
I => data_out,
O => data_out_P,
OB => data_out_N
);
ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFM
component:
PAD symbol “data_out_P” (Pad Signal = data_out_P)
BUFINV symbol “U1/OBUFDS” (Output Signal = data_out_P)
Each of the following constraints specifies an illegal physical site for a
component of type DIFFM:
Symbol “data_out_P” (LOC=D1 [Physical Site Type = DIFFS])
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. Please double check that the types of
logic elements and all of their relevant properties and configuration options
are compatible with the physical site type of the constraint.
Please correct the constraints accordingly.
Only certain pins pairs can be differential pairs. You cannot just use any two IO pins. The list is in the Sparten 3 documentation on the Xilinx website. It varies for each model of the Sparten 3.
Thanks. I do see that. There are P and N’s. Those should be correct.
I am familiar with the Blocks and that only LVDS can be assigned to a certain blocks.
The only question I am asking is how to go about implementing LVDS.
Do I have to use an IBUF_LVDS/OBUF_LVDS as in my previous post, or can I just use LVDS and send the N signal out as inverted?
This way,
data_out_p data_out,
O => data_out_P,
OB => data_out_N
);
Here is an excerpt of XEM3010 functional code using LVDS that may guide you:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity TEST is
Port ( SYS_CLK2 : in std_logic; – main clock
S_RST_N : in std_logic; – async reset
D_RXDATA_P : in std_logic; – serial data from receiver (positive side of diff pair)
D_RXDATA_N : in std_logic; – serial data from receiver (inverted side of diff pair)
S_TXDATA_P : inout std_logic; – serial data to transmitter (positive side of diff pair)
S_TXDATA_N : inout std_logic); – serial data to transmitter (inverted side of diff pair)
end TEST;
architecture Behavioral of TEST is
– some code deleted
IBUFDS_1 : IBUFDS port map (
O => D_RXDATA, – Buffer output
I => D_RXDATA_P, – Diff_p buffer input (connect directly to top-level port)
IB => D_RXDATA_N); – Diff_n buffer input (connect directly to top-level port)
IOBUFDS_1 : IOBUFDS port map (
O => open, – Buffer output
IO => S_TXDATA_P, – Diff_p inout (connect directly to top-level port)
IOB => S_TXDATA_N, – Diff_n inout (connect directly to top-level port)
I => S_SERIAL, – Buffer input
T => ‘0’); – 3-state enable input
end Behavioral;
Excerpt from ucf file :
Assign nets going to RX/TX module
Assign D_RXDATA_N to XBUS34 = JP2_52
NET “D_RXDATA_N” LOC = “J18” | IOSTANDARD = LVDS_25 ;
Assign D_RXDATA_P to XBUS36 = JP2_54
NET “D_RXDATA_P” LOC = “J17” | IOSTANDARD = LVDS_25 ;
Assign S_TXDATA_N to XBUS40 = JP2_60
NET “S_TXDATA_N” LOC = “H17” | IOSTANDARD = LVDS_25 ;
Assign S_TXDATA_P to XBUS38 = JP2_58
NET “S_TXDATA_P” LOC = “H18” | IOSTANDARD = LVDS_25 ;