LVDS, DCI, Mixed standards on a IO bank

I am designing an interface board to the XEM3010 and want to bring in a high speed LVDS clock from a clock generator to the XCLK LVDS input. now the user manual states that the Vcco for bank 1 is set to 3.3V but it is ok for differental inputs because it uses Vccaux instead of Vcco. my question is what about the DCI. the inpedance of the input is usually ties to VccO and gnd, is there no support for DCI for thse XCLK and YCLK inputs?

Also if this is true can the bank3 for example be only LVDS inputs and we can still power Bank 3 with 3.3V and instansate LVDS25 input signals?

Does anyone know if you can have LVDS25 and LVCMOS33 on the same bank of a FPGA?